As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges in both fabrication and design have resulted in the development of three dimensional designs, including a fin-like field effect transistor commonly referred to as a “FinFET”. A typical FinFET is fabricated on a silicon substrate on which silicon is etched into a vertical fin-shaped body extending from the substrate. The channel of the FET is comprised of the vertical fin. The gate is wrapped around and over the fin, providing for a double gate structure that enables gate control of the channel from both sides. Additionally, FinFETs enjoy a reduction in the short channel effect, as well as higher current flow.
In prior art FinFET designs, silicon is used as the channel material, with silicon germanium (“SiGe”) being used as a source/drain (“S/D”) stressor. Unfortunately, silicon has a low electron and hole mobility, making it a less than ideal choice for the channel. Additionally, strain-enhanced performance will become saturated with increasing strain; as a result, there are limits to S/D strain-enhancement.